1. Field
The present invention relates to electronic circuits, and more particularly, to logic circuits.
2. Description of the Related Art
Dynamic circuitry utilizes synchronous logic circuits that generate an output with dynamic signaling characteristics depending upon a predetermined combination of inputs. Such circuitry is typically characterized by two operational phases, a precharge phase and an evaluate phase. In the precharge phase, a node (e.g., a dynamic node) is precharged to a known or predetermined voltage level. In the evaluate phase, a logic array or logic “tree” of transistors is given the opportunity to discharge the node to a second known or predetermined voltage level or to allow the precharge to persist. In some examples, each input is coupled, typically, to a gate (control terminal) of one or more of the transistors in the logic tree. The final charge on the dynamic node may thereby be controlled by the particular values of the inputs and by the way the transistors are coupled within the tree. Conventionally, the final voltage of the dynamic node, high or low, provides the logical output of a dynamic logic gate after being suitably buffered, and perhaps inverted. Each of these two phases correspond to one of the two clock states of a clock signal cycle to which the dynamic circuitry is synchronized. Most examples of a dynamic circuit precharge the node when the clock is low and evaluate the node when the clock is high.
Two common uses for dynamic circuits are as decoders and as comparators. Decoders output a unique signal if and only if all of the bits of an input match a predetermined set of values. A decoder may thereby enable a particular write line in a matrix of memory cells if and only if an input memory address matches,the predetermined address of a line of memory cells. Similarly, a digital comparator will output a unique signal if and only if two sets of inputs, each containing multiple data bits, are identical. Other uses of dynamic circuits devices include tag arrays and select signals in CAM arrays, arithmetic functions, and other types of circuitry, e.g., in which computation of multi-bit NAND, AND, NOR, or OR functions are desirable, e.g., where time-critical wide-ANDing or ORing is desired.
The particular way the inputs are combined within the logic tree of a dynamic circuit device determines the particular operating characteristics, and hence, the particular name of the dynamic circuit device. Any Boolean function can be implemented as a dynamic circuit device by constructing the tree such that the tree causes the dynamic node to discharge when the Boolean function is either true or false, as needed by the designer. When driving static logic, it is not consequential whether a tree allows the charge on a dynamic node to persist when the Boolean function is true or to persist when the function is false, because an inverter can be used to obtain the desired polarity. However, when driving dynamic logic, the polarity is consequential.
A dynamic circuit device can be implemented in one of two logically equivalent ways. The two implementations correspond to a tree that discharges the charged node when the Boolean function is true and to a tree that discharges the charged node when the Boolean function is false. When the dynamic circuit device discharges the node if the Boolean function is true, it is said to “evaluate to the active state.” When the dynamic circuit device discharges the node if the Boolean function is false, it is said to “evaluate to the inactive state.” One of these implementations uses its inputs connected in a manner to describe a particular function. The second implementation uses the complements of the inputs and a second function. DeMorgan's law allows the designer to restructure the tree of the first function to produce a tree for the second function. The second function is the first function's complement.
Although logically equivalent, each of the two possible implementations of a dynamic circuit device has its own disadvantages. Specifically, the more transistors coupled in series within the tree, the slower the performance of the dynamic circuit device. This disadvantage is typically associated with a dynamic circuit device that implements an AND that discharges the charged node when its function is true. Conversely, a dynamic circuit device that evaluates to the inactive state may generate an output unacceptable to many types of circuits such as e.g. a dynamic circuit that discharges the charged node when its function is false.
There is a constant need to provide faster, smaller, and lower power implementations of comparators used in different circuit blocks (e.g., CAMs, cache tag arrays), various arithmetic functions, and selected address decode units. A more robust, larger fan-in, faster logical NAND/NOR and AND/OR circuit is desirable for use in wide comparators or wide zero detect circuits, especially for 32 bit and higher architectures.
Prior approaches have failed to provide a functional NAND output (e.g., a statically driven node with dynamic signaling characteristics without additional buffering), have inherent susceptibility to noise introduced from the output, have failed to handle multiple dynamic evaluation nodes properly and consistently, have failed to recover from miss-evaluations, have failed to provide sufficiently flexible control of the dynamically necessary internal race, and have failed to allow input signals from resetting early.
What is desired is an improved logic circuit.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.